Blogs
Notes on verification, from the archive and as they are written.
22 Feb 2019
Implementing randc behavior using regular constraints in SystemVerilogIn SystemVerilog, variables declared with the randc keyword are random-cyclic variables that cycle through all the values in a random permutation of their declared range.
18 Feb 2019
What is a Verification Test plan?A Verification Test plan is a specification document that captures all the details needed for verifying a given design.
16 Feb 2019
How similar is an ASIC verification job compared to a Software coding profile?An ASIC or SOC Verification job is increasingly becoming like a Software coding and debugging profile.
18 Aug 2018
Verification Engineer Career- Opportunities and PathOne of the big job opportunities in VLSI Design spectrum is front end verification engineer.
15 Aug 2018
VLSI Design – Front End and Back EndIn VLSI design, what is VLSI Front end and what is VLSI Back end ?
29 Jul 2018
Opportunities For Electronics Engineering GraduatesThis week, I got an invite to talk to a batch of final year Electronics Engineering Students who was undergoing a 4 week internship training as part of curriculum.
20 Jul 2018
Verification, Validation, Testing of ASIC and SOC designs – What are the differences?Do you know differences between Verification, Validation and Testing of ASIC / SOC designs in the VLSI/chip design life cycles?
30 Jun 2018
Cracking Digital VLSI Verification Interviews: Interview Success – A unique bookA large number of jobs in semiconductor industry fall in the category of Digital VLSI Design and Verification.
16 May 2018
What makes a great Verification engineer?Is it knowledge about a protocol or an IP ?
Earlier notes from the archive will be added here.