1
SoC Verification Using SystemVerilog
Verification planning, simulation, formal and assertion methods, and directed versus constrained-random testing with coverage. SystemVerilog for testbenches, worked through on an Ethernet switch.
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These self-paced courses are on Udemy. Take them in this order.
2
Learning SystemVerilog Assertions and Functional Coverage
SystemVerilog Assertions, then functional coverage: covergroups, coverpoints, bins, and cross coverage. The coding used in assertion-based and coverage-driven verification.
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Learn to Build OVM/UVM Testbenches from Scratch
OVM and UVM concepts, then testbenches coded from the ground up with examples and assignments. The closing exercise is a UVM environment for the APB bus.
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Cracking Programming Questions
Practice questions for a verification interview: programming basics, object-oriented programming, UNIX and Linux, C and C++, Perl, and Verilog and SystemVerilog. 180 questions, with answers.
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